Title of Project : Cost-Effective Tools for Routing of High-Performance Circuit Interconnects in Nanometric Technology Regime
Objective of the Project
Design Automation algorithms for Integrated Circuit layouts in the Nanometric regime have to deal with issues that are drastically different from those of classical physical design. Recently, circuit performance is largely dominated by the interconnects, which need to be planned well in advance in the design flow taking into account factors like Buffer Placement, Wiring Congestion, Crosstalk, Heat Dissipation and others. This, in turn, helps in reducing the number of iterations in the design to meet specific design requirements.
The objective of this project is to focus on the Nanometric interconnect design integrated with the related issues like buffer placement, congestion, crosstalk, heat dissipation and others. Specifically, our representative target problem would be as follows: Given a placement of logic modules and its associated netlist, construct buffer placement-aware Optimal Routing Trees for all nets such that the routing congestion, crosstalk, and heat dissipation are within specified bounds. Broadly, the aim of this project would be to help Indian research community come up with indigenous cost-effective tools for VLSI layout design.
The proposed research would broadly attempt to
- Analyze critically the existing Global Routing algorithms for the Nanometric circuits.
- Concentrate on the development of practical solutions to have a faster layout design cycle.
- Invent efficient Global Routing algorithm(s) in Nanometric circuits with predictability for congestion, delay, crosstalk, heat dissipation, and buffer placement, and implement them.
Possible significant technology fall-outs of the proposed project:
- New global interconnect routing algorithms taking several critical Nanometric factors into account.
- Achieving faster layout design cycle, if and when the algorithms are embedded in the normal layout design flow.
- Making a successful dent into one of the Grand Challenges Identify Solutions Addressing Global Wiring Issues as mentioned in the Annual Report of the International Technology Roadmap for Semiconductors (ITRS), 2002 (http://www.itrs.net/itrs/publntrs.nsf).
Duration of Project: TWO years (24 months).